1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to a NOR array and a NAND array of electrically programmable memory cells that are flash erasable, wherein both the NOR and NAND arrays are integrated upon a common substrate that can be made of predominantly single crystalline silicon.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
There are numerous types of memories available in the marketplace. For example, large volumes of data can be stored in magnetic memory, such as a hard disk drive. Lesser quantities of data can be stored in memory arranged upon an integrated circuit, oftentimes referred to as “semiconductor memory.” Semiconductor memory is typically arranged closer to the core logic unit or execution unit than the hard disk drive and can be accessed much faster than the disk drive.
Common to semiconductor memory is a storage cell. Typically, storage cells are arranged in an array, with each cell adapted to receive a bit of data. The bit can be written (programmed) into the cell and the programmed bit can be read from the cell. In many instances, however, the bit can remain substantially indefinitely within the cell and may only be read from and not written into the cell. Thus, semiconductor memory can be classified as non-volatile memory or as read-only memory (ROM).
Depending on the application, semiconductor memory can either be volatile memory or non-volatile memory. Moreover, the memory can be either programmed in the field or programmed by the manufacturer. Regardless of the application, however, it is generally recognized that the number of memory cells is usually much greater than the number of logic gates within the core logic unit. This implies that the memory cost per bit must be kept very low in order to make the semiconductor memory economically feasible. One way to do so would be to make the memory device as small as possible.
While static RAMs and dynamic RAMs are generally classified as volatile memories, ROMs are designed as non-volatile memories. ROMs that are programmed by the manufacturer are typically known as masked ROMs. The category of ROMs that are programmed in the field include programmable ROM or PROM, erasable-programmable ROM or EPROM, or electrically-erased programmable ROM or EEPROM.
Most PROMs can only be programmed once, typically by blowing open an appropriate word-to-bit connection path. Conversely, EPROMs and EEPROMs can be programmed and reprogrammed multiple times. EPROMs are programmed by injecting hot electrons into, for example, a floating gate dielectrically spaced above the transistor channel. The injected electrons can thereafter be removed by irradiating the floating gate with ultraviolet light. One advantage of EPROMs is that each cell consists of only one transistor, allowing an EPROM semiconductor memory to be fabricated with significantly high densities. Unfortunately, however, an EPROM must be packaged in a relatively expensive ceramic package with a UV-transparent window. The amount of time needed to erase a programmed cell is also rather significant. Still further, the UV light source will erase the entire EPROM semiconductor device.
Rather than changing the entire device, EEPROMs were developed to enable a user to change one byte at a time. Most conventional EEPROMs implement a floating gate, similar to EPROMs, but use tunnel oxides in order to allow electrons to tunnel onto and from the floating gate. The tunneling process, referred to as Fowler-Nordheim tunneling, is advantageously reversible. While EEPROMs allow individual cells to be erased and programmed, EEPROMs require a select transistor in each cell. Otherwise, the high voltage applied to the drain of the selected cell during an erase cycle would also appear on the drain of the other, unselected cells in the same memory column. The requirement of a select transistor significantly decreases the density and increases the overall manufacturing cost of an EEPROM.
In order to overcome the size constraints of the byte-programmed EEPROM having two transistors per cell, flash EEPROM was developed. While the contents of all of the memory cells or a block of cells can be erased simultaneously as with EPROM, flash does not require a select transistor for each cell. Moreover, a flash memory cell can be erased much more rapidly than an EPROM.
Flash EEPROM typically implements Fowler-Nordheim tunneling to remove electrons programmed into the floating gate. The tunneling mechanism removes those electrons through the tunnel oxide and onto the drain region. However, instead of using Fowler-Nordheim tunneling, the floating gate is programmed by hot electron injection into the gate. Thus, a flash EEPROM can be programmed similar to EPROM, but is generally erased similar to a byte-erasable EEPROM.
The control and floating gates of a single transistor flash EEPROM cell is arranged in an array, with floating gates connected to word lines and the drain node connected to bit lines. More specifically, the drain nodes can be connected either in parallel or in series to the bit lines, depending on whether the array is configured as a NOR-type array or a NAND-type array. In a NOR-type array, the transistor connected to the common bit line is activated by a corresponding word line and the bit line will transition to a power supply, typically ground. Since the logic function is similar to a NOR gate, this arrangement is generally understood to be a NOR-type array or NOR flash in the present instance. Contrary to a NOR array arrangement, a NAND array is one where all transistors connected to the common bit line must be activated before the bit line will transition to the power supply, typically ground.
Conventional flash EEPROM semiconductor memory devices are implemented as either a NOR array or a NAND array. This is primarily due to the desired application. For example, the parallel-operation of a NOR array oftentimes dictates the NOR flash EEPROMs as having faster access time, but longer erasing and programming times. However, a NAND array can advantageously use the tunneling mechanism for both erasing and programming. This provides a much faster erasure and program times than NOR arrays. Thus, while access times are faster in a NOR array, NOR arrays are typically dedicated to applications which require minimal erasure and programming. For example, one such application would be to store the boot-up code of an execution unit. NAND arrays, however, due to their slower access time but faster program and erase times, are better suited for storing non-boot code used for data/file manipulation.
Partially due to the radically different applications in which a flash NOR array and a flash NAND array are slated, conventional flash memory devices implement the dissimilar arrays on separate and distinct integrated circuits. One circuit can be used during boot-up, for example, and the other circuit can be more readily erased and programmed during subsequent data/file manipulation. Moreover, because of the requirement for an internal interface and register indigenous to the flash NAND array, the interface is implemented only on the integrated circuit containing the NAND array. Since a NOR array does not require this interface, the integrated circuit containing the NOR array can simply include the row and column decoders without additional circuit overhead. Thus, the conventional flash EEPROM requires separate integrated circuits for the separate NOR and NAND arrays in order to make the flash EEPROM economically feasible.